A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS
نویسندگان
چکیده
منابع مشابه
SAR ADC in 65 nm CMOS
This paper presents a Successive Approximation Register Analog-to-Digital Converter (SAR ADC) design for sensor applications. An energy-saving switching technique is proposed to achieve ultra low power consumption. The measured Signal-to-Noise-and-Distortion Ratio (SNDR) of the ADC is 58.4 dB at 2 MS/s with an ultra-low power consumption of only 6.6 μW from a 0.8V supply, resulting in a Figure-...
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ژورنال
عنوان ژورنال: IEEE Journal of Solid-State Circuits
سال: 2017
ISSN: 0018-9200,1558-173X
DOI: 10.1109/jssc.2017.2705070